ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 981

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

39.7.7
Name:
Address:
Access:
• SPEED_CFG: Speed Configuration
Speed Configuration:
• TST_J: Test J Mode
0 = no effect.
1 = set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the D+ line.
• TST_K: Test K Mode
0 = no effect.
1 = set to send the K state on the UDPHS line. This enables the testing of the high output drive level on the D- line.
• TST_PKT: Test Packet Mode
0 = no effect.
1 = set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye pat-
terns, jitter, and any other dynamic waveform specifications.
• OPMODE2: OpMode2
0 = no effect.
1 = set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffing and the NRZI encoding.
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Value
0
1
2
3
31
23
15
–
–
–
7
–
UDPHS Test Register
Name
NORMAL
HIGH_SPEED
FULL_SPEED
UDPHS_TST
0x400A40E0
Read-write
30
22
14
–
–
–
6
–
Description2
Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host
supports it and then to automatically switch to High Speed mode
Reserved
Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug
or test purpose.
Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this
configuration, the macro will not respond to a High Speed reset handshake.
OPMODE2
29
21
13
–
–
–
5
TST_PKT
28
20
12
–
–
–
4
TST_K
27
19
11
–
–
–
3
TST_J
26
18
10
–
–
–
2
SAM3U Series
SAM3U Series
25
17
–
–
9
–
1
SPEED_CFG
24
16
–
–
8
–
0
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