ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 111

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.11.5
13.11.5.1
13.11.5.2
13.11.5.3
6430D–ATARM–25-Mar-11
LDR, PC-relative
Syntax
Operation
Restrictions
Load register from memory.
where:
type
cond
Rt
Rt2
label
LDR loads a register with a value from a PC-relative memory address. The memory address is
specified by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and half-
words can either be signed or unsigned. See
label must be within a limited range of the current instruction.
offsets between label and the PC.
Table 13-19. Offset ranges
You might have to use the .W suffix to get the maximum offset range. See
selection” on page
In these instructions:
When Rt is PC in a word load instruction:
Instruction type
Word, halfword, signed halfword, byte, signed
byte
Two words
• Rt can be SP or PC only for word loads
• Rt2 must not be SP and must not be PC
• Rt must be different from Rt2.
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label
B
SB
H
SH
-
is one of:
unsigned byte, zero extend to 32 bits.
signed byte, sign extend to 32 bits.
unsigned halfword, zero extend to 32 bits.
signed halfword, sign extend to 32 bits.
omit, for word.
is an optional condition code, see
is the register to load or store.
is the second register to load or store.
is a PC-relative expression. See
102.
“Address alignment” on page
; Load two words
Offset range
− 4095 to 4095
− 1020 to 1020
“PC-relative expressions” on page
“Conditional execution” on page
Table 13-19
SAM3U Series
99.
shows the possible
“Instruction width
100.
100.
111