IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 103

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Figure 5–18. 64-Bit Avalon-ST tx_st_data Cycle Definition for TLP 4-DWord Header with Non-QWord Aligned Address
Figure 5–19. 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-DWord Header TLP with QWord Aligned Address
Figure 5–20. 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-DWord Header TLP with non-QWord Aligned Address
December 2010 Altera Corporation
tx_st_data[127:96]
tx_st_data[63:32]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[127:96]
tx_st_data[31:0]
tx_st_data[31:0]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[31:0]
Figure 5–18
TLPs for four dword header with non-qword aligned addresses with a 64-bit bus.
Figure 5–19
for a three dword header with qword aligned addresses.
Figure 5–20
for a 3 dword header with non-qword aligned addresses.
tx_st_empty
tx_st_valid
tx_st_empty
tx_st_eop
tx_st_sop
tx_st_eop
tx_st_sop
tx_st_valid
tx_st_sop
tx_st_eop
tx_st_err
clk
clk
clk
illustrates the mapping between Avalon-ST TX packets and PCI Express
shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs
shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs
Header 1
Header 0
Header2
Header1
Header0
Header 2
Header 1
Header 0
Data0
Header3
Header2
Data 2
Data3
Data1
Data0
Data 4
Data 3
Data 2
Data 1
Data0
Data (n-1)
Data (n)
Data1
Data(n-1)
Data2
Data(n)
PCI Express Compiler User Guide
5–19