IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 169

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Reset and Clocks
Clocks
Figure 7–7. PCI Express IP core Clock Domains
Notes to
(1) The 100 MHz refclk can only drive the transceiver.
(2) If the core_clk_out frequency is 125 MHz, you can use this clock signal to drive the cal_blk_clk signal.
December 2010 Altera Corporation
100 MHz
Figure
refclk
(1)
7–7:
Figure 7–7
As
■
■
■
p_clk
The transceiver derives p_clk from the 100 MHz refclk signal that you must provide
to the device. The p_clk frequency is 250 MHz for Gen1 systems and 500 MHz for
Gen2. The PCI Express specification allows a +/- 300 ppm variation on the clock
frequency.
The CDC module implements the asynchronous clock domain crossing between the
PHY/MAC p_clk domain and the data link layer core_clk domain.
Figure 7–7
Stratix IV GX Device
p_clk
core_clk, core_clk_out
pld_clk
Trans-
ceiver
User Application
illustrates the clock domains.
p_clk
indicates, there are three clock domains:
PCI Express Hard IP - Three Clock Domains
MAC
PHY
Crossing
Domain
Clock
(CDC)
Data Link
core_clk_out
Layer
(DLL)
÷
2
core_clk
Transaction
(128-bit mode only)
Layer
(TL)
User Clock
Domain
PCI Express Compiler User Guide
pld_clk
Adapter
7–9