IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 47

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
PCI Registers
Table 3–2. PCI Registers (Part 1 of 2)
December 2010 Altera Corporation
BAR Table (BAR0)
BAR Table (BAR1)
BAR Table (BAR2)
BAR Table (BAR3)
BAR Table (BAR4)
BAR Table (BAR5)
BAR Table (EXP-ROM)
Device ID
0x000
Subsystem ID
0x02C (3)
Revision ID
0x008
Vendor ID
0x000
(3)
(3)
(3)
(3)
(4)
Parameter
In the SOPC Builder design flow, you can choose to allow SOPC Builder to
automatically compute the BAR sizes and Avalon-MM base addresses or to enter the
values manually. The Avalon-MM address is the translated base address
corresponding to a BAR hit of a received request from PCI Express link. Altera
recommends using the Auto setting. However, if you decide to enter the address
translation entries, then you must avoid a conflict in address assignment when
adding other components, making interconnections, and assigning base addresses in
SOPC Builder. This process may take a few iterations between SOPC builder address
assignment and MegaWizard address assignment to resolve address conflicts.
BAR type and size
BAR type and size
BAR type and size
BAR type and size
BAR type and size
BAR type and size
Disable/Enable
0x0004
0x0004
0x01
0x1172
PCI Base Address Registers (0x10, 0x14, 0x18, 0x1C, 0x20, 0x24)
Value
PCIe Read-Only Registers
BAR0 size and type mapping (I/O space (1), memory space). BAR0
and BAR1 can be combined to form a 64-bit prefetchable BAR. BAR0
and BAR1 can be configured separate as 32-bit non-prefetchable
memories.)
BAR1 size and type mapping (I/O space (1), memory space. BAR0
and BAR1 can be combined to form a 64-bit prefetchable BAR. BAR0
and BAR1 can be configured separate as 32-bit non-prefetchable
memories.)
BAR2 size and type mapping (I/O space (1), memory space. BAR2
and BAR3 can be combined to form a 64-bit prefetchable BAR. BAR2
and BAR3 can be configured separate as 32-bit non-prefetchable
memories.)
BAR3 size and type mapping (I/O space (1), memory space. BAR2
and BAR3 can be combined to form a 64-bit prefetchable BAR. BAR2
and BAR3 can be configured separate as 32-bit non-prefetchable
memories.)
BAR4 size and type mapping (I/O space (1), memory space. BAR4
and BAR5 can be combined to form a 64-bit BAR. BAR4 and BAR5
can be configured separate as 32-bit non-prefetchable
memories.)
BAR5 size and type mapping (I/O space (1), memory space. BAR4
and BAR5 can be combined to form a 64-bit BAR. BAR4 and BAR5
can be configured separate as 32-bit non-prefetchable memories.)
Expansion ROM BAR size and type mapping (I/O space, memory
space, non-prefetchable).
Sets the read-only value of the device ID register.
Sets the read-only value of the subsystem device ID register.
Sets the read-only value of the revision ID register.
Sets the read-only value of the vendor ID register. This parameter
can not be set to 0xFFFF per the PCI Express Specification.
(2)
(2)
(2)
Description
PCI Express Compiler User Guide
3–5