IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 176

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–16
PCI Express Compiler User Guide
Table 7–2
Table 7–2. Selecting the Avalon Clock Domain
Use PCIe core clock
Use separate clock
Avalon Clock Domain
summarizes the differences between the two Avalon clock modes.
In this clocking mode, the PCI Express IP core provides a 125 MHz
clock output to be used as a system clock and the IP core protocol
layers operate on the same clock. This clock is visible to SOPC
Builder and can be selected as the clock source for any Avalon-MM
component in the system.
In this clocking mode, the PCI Express IP core’s Avalon-MM logic
operates on an external clock source while the IP core protocol
layers operate on an internally generated clock.
Description
December 2010 Altera Corporation
Chapter 7: Reset and Clocks
Clocks