IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 90

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–6
Table 5–1. Signal Groups in the PCI Express IP core with Avalon-ST Interface
PCI Express Compiler User Guide
Signal Group
Avalon-ST RX
Avalon-ST TX
Clock
Clock
Reset and link training
ECC error
Interrupt
Interrupt and global error
Configuration space
Configuration space
LMI
PCI Express
reconfiguration block
Power management
Completion
Transceiver control
Serial
PIPE
Test
Test
Note to
(1) Provided for simulation only
Table
5–1:
Table 5–1
links to the subsequent sections that describe each interface.
point
End
v
v
v
v
v
v
v
v
v
v
v
v
v
v
—
—
—
—
(1)
Hard IP
lists the interfaces of both the hard IP and soft IP implementations with
Root
Port
v
v
v
—
v
v
v
v
v
v
v
v
v
v
v
—
—
(1)
—
Soft
IP
v
v
—
v
v
—
v
—
—
v
—
—
v
v
v
v
v
v
“64-, 128-, or 256-Bit Avalon-ST RX Port” on page 5–7
“64-, 128-, or 256-Bit Avalon-ST TX Port” on page 5–13
“Clock Signals—Hard IP Implementation” on page 5–23
“Clock Signals—Soft IP Implementation” on page 5–23
“Reset and Link Training Signals” on page 5–24
“ECC Error Signals” on page 29
“PCI Express Interrupts for Endpoints” on page 5–29
“PCI Express Interrupts for Root Ports” on page 5–31
“Configuration Space Signals—Hard IP Implementation” on page 5–31
“Configuration Space Signals—Soft IP Implementation” on page 5–39
“LMI Signals—Hard IP Implementation” on page 5–40
“PCI Express Reconfiguration Block Signals—Hard IP
Implementation” on page 5–41
“Power Management Signals” on page 5–42
“Completion Side Band Signals” on page 5–44
“Transceiver Control” on page 5–53
“Serial Interface Signals” on page 5–55
“PIPE Interface Signals” on page 5–56
“Test Interface Signals—Hard IP Implementation” on page 5–59
“Test Interface Signals—Soft IP Implementation” on page 5–60
Physical
Logical
Test
Description
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Avalon-ST Interface