IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 202

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

12–2
Physical Layer Errors
Table 12–2. Errors Detected by the Physical Layer
Data Link Layer Errors
Table 12–3. Errors Detected by the Data Link Layer
PCI Express Compiler User Guide
Receive port error
Note to
(1) Considered optional by the PCI Express specification.
Bad TLP
Bad DLLP
Replay timer
Replay num rollover
Data link layer protocol
Table
Error
Error
12–2:
Table 12–2
Table 12–3
Correctable
Correctable
Correctable
Correctable
Uncorrectable
(fatal)
Correctable
describes errors detected by the physical layer.
describes errors detected by the data link layer.
Type
Type
This error has the following 3 potential causes:
■
■
■
This error occurs when a LCRC verification fails or when a sequence
number error occurs.
This error occurs when a CRC verification fails.
This error occurs when the replay timer times out.
This error occurs when the replay number rolls over.
This error occurs when a sequence number specified by the
AckNak_Seq_Num does not correspond to an unacknowledged TLP.
Physical coding sublayer error when a lane is in L0 state. These errors
are reported to the core via the per lane PIPE interface input receive
status signals, rxstatus<lane_number>_ext[2:0] using the
following encodings:
100: 8B10B Decode Error
101: Elastic Buffer Overflow
110: Elastic Buffer Underflow
111: Disparity Error
Deskew error caused by overflow of the multilane deskew FIFO.
Control symbol received in wrong lane.
(Note 1)
Description
Description
December 2010 Altera Corporation
Chapter 12: Error Handling
Physical Layer Errors