IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 174

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–14
PCI Express Compiler User Guide
Avalon-MM Interface–Hard IP and Soft IP Implementations
Clocking for a Generic PIPE PHY and the Simulation Testbench
Figure 7–11
configuration is also used for simulation. As this figure illustrates the 100 MHz
reference clock drives the input to a PLL which creates a 125 MHz clock for both the
PCI Express IP core and the application logic.
Figure 7–11. Clocking for the Generic PIPE Interface and the Simulation Testbench, All Device
Families
When using the PCI Express IP core with an Avalon-MM application interface in the
SOPC Builder design flow, the clocking is the same for both the soft IP and hard IP
implementations. The clocking requirements explained in the previous sections
remain valid. The PCI Express IP core with Avalon-MM interface supports two
clocking modes:
■
■
When you turn on the
page of the parameter editor, the system clock source, labeled ref_clk in
is external to the PCI Express IP core. The protocol layers of the IP core are driven by
an internal clock that is generated from the reference clock, ref_clk. The PCI Express
IP core exports a 125 MHz clock, clk125_out, which can be used for logic outside the
IP core. This clock is not visible to SOPC Builder and therefore cannot drive other
Avalon-MM components in the system.
Clock Source
Separate PCI Express and Avalon clock domains
Single PCI Express core clock as the system clock for the Avalon-MM clock domain
100-MHz
illustrates the clocking when the PIPE interface is used. The same
<variant> .v or .vhd - For Simulation
Use separate clock
refclk
pld_clk
pll_inclk
(PCIe MegaCore Function)
<variant> _core.v or .vhd
option on the
PLL
core_clk_out
clk125_out
Avalon Configuration Settings
December 2010 Altera Corporation
Chapter 7: Reset and Clocks
Application Clock
Figure
7–12,
Clocks