IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 311

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter :
Descriptor/Data Interface
Table B–2. RX Descriptor Phase Signals (Part 2 of 2)
Table B–4. RX Data Phase Signals (Part 1 of 2)
December 2010 Altera Corporation
rx_mask<n>
Note to
(1) For all signals, <n> is the virtual channel number which can be 0 or 1.
rx_dfr<n>
rx_dv<n>
Table
Signal
Signal
(1)
B–2:
(1)
The IP core generates the eight MSBs of this signal with BAR decoding information.
Refer to
Table B–3. rx_desc[135:128]: Descriptor and BAR Decoding
Table B–4
Note to
(1) Only one bit of [135:128] is asserted at a time.
I/O
I/O
I
Table
O
O
Table
128
129
130
131
132
133
134
135
Bit
describes the data phase signals.
Receive mask (non-posted requests). This signal is used to mask all non-posted
request transactions made to the application interface to present only posted and
completion transactions. This signal must be asserted with rx_retry<n> and
deasserted when the IP core can once again accept non-posted requests.
Receive data phase framing. This signal is asserted on the same or subsequent clock
cycle as rx_req to request a data phase (assuming a data phase is needed). It is
deasserted on the clock cycle preceding the last data phase to signal to the application
layer the end of the data phase. The application layer does not need to implement a
data phase counter.
Receive data valid. This signal is asserted by the IP core to signify that
rx_data[63:0] contains data.
B–3:
B–3.
= 1: BAR 0 decoded
= 1: BAR 1 decoded
= 1: BAR 2 decoded
= 1: BAR 3 decoded
= 1: BAR 4 decoded
= 1: BAR 5 decoded
= 1: Expansion ROM decoded
Reserved
Description
Description
Type 0 Component
(Note 1)
PCI Express Compiler User Guide
B–5