IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 247

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Test Driver Module
Table 15–14. Write Descriptor 0
December 2010 Altera Corporation
DW0
DW1
0x810
0x814
Shared Memory
Offset in BFM
For a root port Verilog HDL file, see:
<variation_name>_examples/rootport/testbench/altpcietb_bfm_driver_rp.v
The BFM test driver module performs the following steps in sequence:
1. Configures the root port and endpoint configuration spaces, which the BFM test
2. Finds a suitable BAR to access the example endpoint design control register space.
3. If a suitable BAR is found in the previous step, the driver performs the following
DMA Write Cycles
The procedure dma_wr_test used for DMA writes uses the following steps:
1. Configures the BFM shared memory. Configuration is accomplished with three
driver module does by calling the procedure ebfm_cfg_rp_ep, which is part of
altpcietb_bfm_configure.
Either BARs 2 or 3 must be at least a 256-byte memory BAR to perform the DMA
channel test. The find_mem_bar procedure in the altpcietb_bfm_driver_chaining
does this.
tasks:
■
a. The chaining DMA writes the EPLast bit of the
b. The chaining DMA issues an MSI when the last descriptor has completed.
■
c. The chaining DMA writes the EPLast bit of the
d. The chaining DMA issues an MSI when the last descriptor has completed.
e. The data written back to BFM is checked against the data that was read from
f. The driver programs the chaining DMA to perform a test that demonstrates
descriptor tables
DMA read—The driver programs the chaining DMA to read data from the
BFM shared memory into the endpoint memory. The descriptor control fields
(Table
steps to indicate transfer completion:
Table” on page 15–17
descriptors.
DMA write—The driver programs the chaining DMA to write the data from its
endpoint memory back to the BFM shared memory. The descriptor control
fields
following steps to indicate transfer completion:
Table” on page 15–17
descriptors.
the BFM.
downstream access of the chaining DMA endpoint memory.
82
3
(Table
15–6) are specified so that the chaining DMA completes the following
Value
15–6) are specified so that the chaining DMA completes the
(Table
15–14,
after finishing the data transfer for the first and last
after completing the data transfer for the first and last
Transfer length in DWORDS and control bits as described in
Table 15–6 on page 15–14
Endpoint address
Table
15–15, and
Table
Description
“Chaining DMA Descriptor
“Chaining DMA Descriptor
15–16).
PCI Express Compiler User Guide
15–19