IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 343

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Avalon-ST Interface
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
Arria GX Devices
f
The following sections show the resource utilization for the soft IP implementation of
the PCI Express IP Core. It includes performance and resource utilization numbers for
the following application interfaces:
■
■
■
Refer to
performance and resource utilization of the hard IP implementation.
This section provides performance and resource utilization for the soft IP
implementation of following device families:
■
■
■
■
■
Table C–1
Arria GX (EP1AGX60DF780C6) devices for different parameters with a maximum
payload of 256 bytes using the Quartus II software, version 10.1.
Table C–1. Performance and Resource Utilization, Avalon-ST Interface–Arria GX Devices
Note to
(1) This configuration only supports Gen1.
(Note 1)
×1/ ×4
Avalon-ST Interface
Avalon-MM Interface
Avalon-MM Interface
Arria GX Devices
Arria II GX Devices
Stratix II GX Devices
Stratix III Family
Stratix IV Family
×1
×1
×4
×4
Table
Performance and Resource Utilization
shows the typical expected performance and resource utilization of
Clock (MHz)
C–1:
Parameters
Internal
125
125
125
125
C. Performance and Resource Utilization
Channel
Virtual
1
2
1
2
Combinational
ALUTs
5900
7400
7400
9000
in
Soft IP Implementation
Chapter 1, Datasheet
Registers
Logic
4100
5300
5100
6200
Size
PCI Express Compiler User Guide
M512
Memory Blocks
2
3
6
7
for
M4K
13
17
17
25