IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 85
IP-AGX-PCIE/4
Manufacturer Part Number
IP-AGX-PCIE/4
Description
IP CORE - PCI Express X1 And X4 Lanes For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Avalon-ST Interface
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
1
This chapter describes the signals that are part of the PCI Express IP core for each of
the following primary configurations:
■
■
■
■
■
■
Altera does not recommend the Descriptor/Data interface for new designs.
The main functional differences between the hard IP and soft IP implementations
using an Avalon-ST interface are the configuration and clocking schemes. In addition,
the hard IP implementation offers a 128-bit Avalon-ST bus for some configurations. In
128-bit mode, the streaming interface clock, pld_clk, is one-half the frequency of the
core clock, core_clk, and the streaming data width is 128 bits. In 64-bit mode, the
streaming interface clock, pld_clk, is the same frequency as the core clock, core_clk,
and the streaming data width is 64 bits.
Figure
cores that use the Avalon-ST interface.
Signals in the Hard IP Implementation Root Port with Avalon-ST Interface Signals
Signals in the Hard IP Implementation Endpoint with Avalon-ST Interface
Signals in the Soft IP Implementation with Avalon-ST Interface
Signals in the Hard IP Implementation with Avalon-ST Interface for
Stratix V Devices
Signals in the SOPC Builder Soft or Hard Full-Featured IP Core with Avalon-MM
Interface
Signals in the Completer-Only, Single Dword, IP Core with Avalon-MM Interface
5–1,
Figure
5–2,
Figure
5–3, and
Figure 5–4
illustrate the top-level signals for IP
5. IP Core Interfaces
PCI Express Compiler User Guide
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