IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 307

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Descriptor/Data Interface
Figure B–1. PCI Express IP core with Descriptor/Data Interface
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
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tx_desc
tx_data
rx_desc
rx_data
This chapter describes the PCI Express IP core that employs the legacy
descriptor/data interface. It includes the following sections:
■
■
Altera recommends choosing the Avalon-ST or Avalon-MM interface for all new
designs for compatibility with the hard IP implementation of the PCI Express IP core.
When you use the MegaWizard Plug-In Manager to generate a PCI Express endpoint
with the descriptor/data interface, the MegaWizard interface generates the
transaction, data link, and PHY layers.
RX and TX ports use a data/descriptor style interface, which presents the application
with a descriptor bus containing the TLP header and a separate data bus containing
the TLP payload. A single-cycle-turnaround handshaking protocol controls the
transfer of data.
Descriptor/Data Interface
Incremental Compile Module for Descriptor/Data Examples
To Application Layer
PCI Express MegaCore Function
With information sent
by the application
layer, the transaction
layer generates a TLP,
which includes a
header and, optionally,
a data payload.
The transaction layer
disassembles the
transaction and
transfers data to the
application layer in a
form that it recognizes.
Transaction Layer
The data link layer
ensures packet
integrity, and adds a
sequence number and
link cyclic redundancy
code (LCRC) check to
the packet.
The data link layer
verifies the packet's
sequence number and
checks for errors.
Data Link Layer
B. PCI Express IP Core with the
Figure B–1
Descriptor/Data Interface
The physical layer
encodes the packet
and transmits it to the
receiving device on the
other side of the link.
The physical layer
decodes the packet
and transfers it to the
data link layer.
Physical Layer
illustrates this interface.
To Link
PCI Express Compiler User Guide
Tx
Rx