IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 315

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter :
Descriptor/Data Interface
Figure B–7. RX Aborted Transaction Waveform
December 2010 Altera Corporation
Descriptor
Signals
Data
Signals
rx_desc[135:128]
rx_desc[127:64]
rx_data[63:32]
rx_desc[63:0]
rx_data[31:0]
Transaction Aborted
In
determined it will never be able to accept the transaction layer packet, the application
layer discards it by asserting rx_abort. An alternative design might implement logic
whereby all transaction layer packets are accepted and, after verification, potentially
rejected by the application layer. An advantage of asserting rx_abort is that
transaction layer packets with data payloads can be discarded in one clock cycle.
Having aborted the first transaction layer packet, the IP core can transmit the second,
a three DWORD completion in this case. The IP core does not treat the aborted
transaction layer packet as an error and updates flow control credits as if the
transaction were acknowledged. In this case, the application layer is responsible for
generating and transmitting a completion with completer abort status and to signal a
completer abort event to the IP core configuration space through assertion of cpl_err.
In clock cycle 6, rx_abort is asserted and transmission of the next transaction begins
on clock cycle number.
rx_be[7:0]
Transaction with Data Payload
In
second memory write request of three DWORDS. Bit 2 of rx_data[63:0] is set to 0 for
the completion transaction and to 1 for the memory write request transaction.
rx_mask
rx_abort
rx_retry
Figure
Figure
rx_ack
rx_req
rx_ws
rx_dfr
rx_dv
clk
B–7, a memory read of 16 DWORDS is sent to the application layer. Having
B–8, the IP core receives a completion transaction of eight DWORDS and a
1
2
MEMRD 16 DW
3
valid
valid
4
5
6
7
8
CPL 3 DW
9
valid
valid
PCI Express Compiler User Guide
DW 0
DW 1
0xFF
11
DW 2
0x0F
B–9