IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 301

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

TLP Packet Format without Data Payload
Table A–2. Memory Read Request, 32-Bit Addressing
Table A–3. Memory Read Request, Locked 32-Bit Addressing
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
Byte 0
Byte 4
Byte 8
Byte 12
Byte 0
Byte 4
+0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
0 0 0 0 0 0 0 0 0
+0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
0 0 0 0 0 0 0 1 0 TC
Table A–2
When these headers are transferred to and from the IP core as tx_desc and rx_desc,
the mapping shown in
Table A–1. Header Mapping
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Byte 10
Byte 11
Byte 12
Byte 13
Byte 14
Byte 15
Requester ID
Requester ID
through
+1
+1
TC
Header Byte
A–3
A. Transaction Layer Packet (TLP) Header
0 0 0 0 TD
Table A–1
0 0 0 0 TD EP Attr
show the header format for TLPs without a data payload.
Address[31:2]
+2
Reserved
is used
+2
6
EP
6
5
Attr
127:120
119:112
111:104
103:96
95:88
87:80
79:72
71:64
63:56
55:48
47:40
39:32
31:24
23:16
15:8
7:0
Tag
5 4 3 2 1 0 7 6 5 4 3 2 1 0
4
Tag
3 2 1 0 7 6 5
0 0
0 0 Length
tx_desc/rx_desc Bits
+3
PCI Express Compiler User Guide
Last BE
+3
Last BE
Length
4
Formats
3
First BE
First BE
2
1
0
0
0