IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 150

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–6
Table 6–9. Virtual Channel Capability Structure, Rev2 Spec: Virtual Channel Capability (Part 2 of 2)
Table 6–10. PCI Express Advanced Error Reporting Extended Capability Structure, Rev2 Spec: Advanced Error Reporting
Capability
PCI Express Avalon-MM Bridge Control Register Content
PCI Express Compiler User Guide
0x168
Note to
(1) Refer to
0x800
0x804
0x808
0x80C
0x810
0x814
0x818
0x81C
0x82C
0x830
0x834
Note to
(1) Refer to
registers and the
Base Specification 2.0.
Byte Offset
Byte Offset
Table
Table
Table 6–23 on page 6–12
Table 6–23 on page 6–12
6–9:
6–10:
PCI Express Base Specification 2.0.
Table 6–10
structure.
Control and status registers in the PCI Express Avalon-MM bridge are implemented
in the CRA slave module. The control registers are accessible through the Avalon-MM
slave port of the CRA slave module. This module is optional; however, you must
include it to access the registers.
The control and status register space is 16KBytes. Each 4 KByte sub-region contains a
specific set of functions, which may be specific to accesses from the PCI Express root
complex only, from Avalon-MM processors only, or from both types of processors.
Because all accesses come across the system interconnect fabric —requests from the
PCI Express IP core are routed through the interconnect fabric— hardware does not
enforce restrictions to limit individual processor access to specific regions. However,
the regions are designed to enable straight-forward enforcement by processor
software.
VC Resource Control Register (7)
PCI Express Enhanced Capability Header
Uncorrectable Error Status Register
Uncorrectable Error Mask Register
Uncorrectable Error Severity Register
Correctable Error Status Register
Correctable Error Mask Register
Advanced Error Capabilities and Control Register
Header Log Register
Root Error Command
Root Error Status
Error Source Identification Register
for a comprehensive list of correspondences between the configuration space
for a comprehensive list of correspondences between the configuration space registers and the
31:24
31:24
describes the PCI Express advanced error reporting extended capability
23:16
23:16
Correctable Error Source ID Register
PCI Express Avalon-MM Bridge Control Register Content
15:8
15:8
December 2010 Altera Corporation
Chapter 6: Register Descriptions
7:0
7:0
PCI Express