IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 81

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
PCI Express Avalon-MM Bridge
Figure 4–12. Avalon-MM-to-PCI Express Address Translation
Notes to
(1) N is the number of pass-through bits.
(2) M is the number of Avalon-MM address bits.
(3) P is the number of PCI Express address bits.
(4) Q is the number of translation table entries.
(5) Sp[1:0] is the space indication for each entry.
December 2010 Altera Corporation
Figure
4–12:
31
Slave Base
Address
Avalon-MM Address
Figure 4–12
Generation of PCI Express Interrupts
The PCI Express Avalon-MM bridge supports MSI or legacy interrupts. The completer
only, single dword variant includes an interrupt generation module. For other
variants using the Avalon-MM interface, interrupt support requires instantiation of
the CRA slave module where the interrupt registers and control logic are
implemented.
The RX master module port has an Avalon-MM interrupt (RXmlrq_i) input. Assertion
of this signal or a PCI Express mailbox register write access sets a bit in the PCI
Express interrupt status register and generates a PCI Express interrupt, if enabled.
Software can enable the
Registers”
Enable Register Address: 0x3070”
asserted, the IRQ vector is written to the
Register Address: 0x3060” on page
this register and decides priority on servicing requested interrupts. After servicing the
interrupt, software must clear the appropriate serviced interrupt status bit and
ensure that no other interrupts are pending. For interrupts caused by
Avalon-MM Interrupt Status Register Address: 0x3060”
bits should be cleared in the
Address:
should be cleared in the other Avalon peripheral that sourced the interrupt. This
sequence prevents interrupts from being lost during interrupt servicing.
M
M-1
High Avalon-MM Address
High
control register port
Table updates from
Bits Index table
N N-1
0x3060”. For interrupts due to the RXmIrq_i signal, the interrupt status
by writing to the PCI Express
depicts the Avalon-MM-to-PCI Express address translation process.
Low
0
PCIe Address Q-1
“PCI Express to Avalon-MM Interrupt Status and Enable
(Q entries by P-N bits wide)
Avalon-MM-to-PCI Express
PCIe Address 0
PCIe Address 1
Address Translation Table
Low address bits unchanged
“PCI Express to Avalon-MM Interrupt Status Register
through the CRA slave. When the IRQ input is
(Note 1) (2) (3) (4) (5)
6–11, accessible by the CRA slave. Software reads
SpQ-1
Sp0
Sp1
“PCI Express to Avalon-MM Interrupt Status
“PCI Express to Avalon-MM Interrupt
PCI Express address from Table Entry
becomes High PCI Express address bits
PCI Express Address
P-1
High
mailbox writes, the status
Space Indication
PCI Express Compiler User Guide
N N-1
Low
“PCI Express to
0
4–23