IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 46

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–4
Table 3–1. System Settings Parameters (Part 4 of 4)
PCI Registers
PCI Express Compiler User Guide
Test out width
PCIe reconfig
Note to
(1) When you configure the ALT2GXB transceiver for an Arria GX device, the Currently selected device family entry is Stratix II GX. However you
must make sure that any transceiver settings applied in the ALT2GX parameter editor are valid for Arria GX, otherwise errors will result during
Quartus II compilation.
Parameter
Table
3–1:
The ×1 and ×4 IP cores support memory space BARs ranging in size from 128 bytes to
the maximum allowed by a 32-bit or 64-bit BAR. The ×8 IP cores support memory
space BARs from 4 KBytes to the maximum allowed by a 32-bit or 64-bit BAR.
The ×1 and ×4 IP cores in legacy endpoint mode support I/O space BARs sized from
16 Bytes to 4 KBytes. The ×8 IP core only supports I/O space BARs of 4 KBytes.
The SOPC Builder flow supports the following functionality:
■
■
■
■
■
■
0, 9, 64, 128 or 512
bits
Enable/Disable
Native endpoint, with no support for:
■
■
16 Tags
1 Message Signaled Interrupts (MSI)
1 virtual channel
Up to 256 bytes maximum payload
×1 and ×4 lane width
I/O space BAR
32-bit prefetchable memory
Value
Indicates the width of the test_out signal. The following widths are
possible:
Most of these signals are reserved. Refer to
for more information.
Altera recommends the 64-bit width for the hard IP implementation.
Enables reconfiguration of the hard IP PCI Express read-only
configuration registers. This parameter is only available for the hard IP
implementation.
Hard IP test_out width: None, 9 bits, or 64 bits
Soft IP ×1 or ×4 test_out width: None, 9 bits, or 512 bits
Soft IP ×8 test_out width: None, 9 bits, or 128 bits
Description
December 2010 Altera Corporation
Table 5–35 on page 5–59
Chapter 3: Parameter Settings
PCI Registers