IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 135

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-MM Application Interface
Table 5–27. Avalon-MM TX Slave Interface Signals
Table 5–28. Avalon-MM Clock Signals
December 2010 Altera Corporation
TxsChipSelect_i
TxsRead_i
TxsWrite_i
TxsAddress_i[TXS_ADDR_WIDTH-1:0]
TxsBurstCount_i[9:0]
TxsWriteData_i[63:0]
TxsByteEnable_i[7:0]
TxsReadDataValid_o
TxsReadData_o[63:0]
TxsWaitRequest_o
refclk
clk125_out
AvlClk_i
Clock Signals
Signal SOPC Builder
Signal SOPC Builder
Table 5–27
Table 5–28
Builder.
Refer to
for a complete explanation of the clocking scheme.
“Avalon-MM Interface–Hard IP and Soft IP Implementations” on page 7–14
lists the TX slave interface ports.
describes the clock signals for the PCI Express IP cores generated in SOPC
I/O
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The system interconnect fabric asserts this signal to select the TX
slave port.
Read request asserted by the system interconnect fabric to
request a read.
Read request asserted by the system interconnect fabric to
request a write.
Address of the read or write request from the external Avalon-MM
master. This address translates to 64-bit or 32-bit PCI Express
addresses based on the translation table. The TXS_ADDR_WIDTH
value is determined when the system is created.
Asserted by the system interconnect fabric indicating the amount
of data requested. This count is limited to 4 KBytes, the
maximum data payload supported by the PCI Express protocol.
slave port.
Write byte enable for data.
Asserted by the bridge to indicate that read data is valid.
The bridge returns the read data on this bus when the RX read
completions for the read have been received and stored in the
internal buffer.
buffer space.
Asserted by the bridge to hold off write data when running out of
Write data sent by the external Avalon-MM master to the TX
An external clock source. When you turn on the Use separate
clock option on the Avalon Configuration page, the PCI Express
protocol layers are driven by an internal clock that is generated
from refclk.
This clock is exported by the PCI Express IP core. It can be used
for logic outside of the IP core. It is not visible to SOPC Builder
and cannot be used to drive other Avalon-MM components in the
system.
Avalon-MM global clock. clk connects to AvlClk_i which is the
main clock source of the SOPC Builder system. clk is user-
specified. It can be generated on the PCB or derived from other
logic in the system.
Description
Description
PCI Express Compiler User Guide
5–51