IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 200

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

11–6
PCI Express Compiler User Guide
You can also control the maximum amount of outstanding read request data. This
amount is limited by the number of header tag values that can be issued by the
application and by the maximum read request size that can be issued. The number of
header tag values that can be in use is also limited by the PCI Express IP core. For the
×8 function, you can specify 32 tags. For the ×1 and ×4 functions, you can specify up
to 256 tags, though configuration software can restrict the application to use only 32
tags. In commercial PC systems, 32 tags are typically sufficient to maintain optimal
read throughput.
December 2010 Altera Corporation
Throughput of Non-Posted Reads
Chapter 11: Flow Control