IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 164

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–4
Figure 7–3. Global Reset Signals for ×1 and ×4 Endpoints in the Soft IP Implementation
Notes to
(1) The Gen1 ×8 does not include the crst signal and rstn replaces srst in the soft IP implementation.
(2) The dlup_exit signal should cause the application to assert srst, but not crst.
(3) gxb_powerdown stops the generation of core_clk_out for hard IP implementations and clk125_out for soft IP implementations.
(4) The rx_freqlocked signal is only used for the Gen2 ×4 and Gen2 ×8 PCI Express IP cores.
Reset in Stratix V Devices
PCI Express Compiler User Guide
Other Power
On Reset
perst#
Figure
7–3:
The PCI Express specification defines the following three reset types:
■
■
■
Fundamental (cold) reset—A hardware mechanism for resetting the PCIe IP core
following power on. The perst_n initiates this reset.
Warm reset—A hardware mechanism for resetting the PCIe IP core without
cycling the power supply.
Hot reset—A reset propagated across a Link using a Physical Layer mechanism.
rx_freqlocked
Reset Synchronization
Circuitry from Design
Example
Note (1)
Note (4)
Note (1)
srst
crst
npor
<variant> .v or .vhd
<variant>_ core.v or .vhd
altpcie_hip_pipen1b.v or .vhd
pll_powerdown
gxb_powerdown
pll_locked
rx_pll_locked
<variant> _serdes.v or .vhd
tx_digitalreset
rx_analogreset
rx_digitalreset
Note (3)
SERDES Reset Controller
Note (2)
rx_analogreset
tx_digitalreset
rx_digitalreset
rx_freqlocked
rx_pll_locked
dl_ltssm[4:0]
hotrst_exit
pll_locked
December 2010 Altera Corporation
dlup_exit
l2_exit
Chapter 7: Reset and Clocks
Reset in Stratix V Devices