IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 44

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–2
Table 3–1. System Settings Parameters (Part 2 of 4)
PCI Express Compiler User Guide
PHY Type (continued)
PHY interface
Configure transceiver
block
Lanes
Parameter
HardCopy IV GX
Arria GX
Arria II GX
Arria II GZ
TI XIO1100
NXP PX1011A
16-bit SDR,
16-bit SDR w/TXClk,
8-bit DDR,
8-bit DDR w/TXClk,
8-bit DDR/SDR
w/TXClk,
8 bit SDR,
8-bit SDR w/TXClk,
serial
×1, ×4, ×8
Value
Serial interface where HardCopy IV GX uses the HardCopy IV GX device
family's built-in transceiver to support PCI Express Gen1 and Gen2 ×1,
×4, and ×8. For designs that may target HardCopy IV GX, the
HardCopy IV GX setting must be used even when initially compiling for
Stratix IV GX devices. This procedure ensures HardCopy IV GX
compatible settings in the Stratix IV GX implementation. For Gen2 ×8
variations, this procedure will set the RX Buffer and Retry Buffer to be
only 8 KBytes which is the HardCopy IV GX compatible implementation.
Serial interface where Arria GX uses the Arria GX device family’s built-in
transceiver. Selecting this PHY allows only a serial PHY interface with
the lane configuration set to Gen1 ×1 or ×4.
Serial interface where Arria II GX uses the Arria II GX device family's
built-in transceiver to support PCI Express Gen1 ×1, ×4, and ×8.
Serial interface where Arria II GZ uses the Arria II GZ device family's
built-in transceiver to support PCI Express Gen1 ×1, ×4, and ×8, Gen2
×1, Gen2 ×4.
TI XIO1100 uses an 8-bit DDR/SDR with a TXClk or a 16-bit SDR with a
transmit clock PHY interface. Both of these options restrict the number
of lanes to ×1. This option is only available for the soft IP
implementation.
Philips NPX1011A uses an 8-bit SDR with a TXClk and a PHY interface.
This option restricts the number of lanes to ×1. This option is only
available for the soft IP implementation.
Selects the specific type of external PHY interface based on the interface
datapath width and clocking mode. Refer to
for additional detail on specific PHY modes.
The external PHY setting only applies to the soft IP implementation.
Clicking this button brings up the ALTGX parameter editor allowing you
to access a much greater subset of the transceiver parameters than was
available in earlier releases. The parameters that you can access are
different for the soft and hard IP versions of the PCI Express IP core and
may change from release to release.
For Arria II GX, Cyclone IV GX, Stratix II GX, and Stratix IV GX, refer to
the “Protocol Settings for PCI Express (PIPE)” in the
Setup Guide
You do not need to change any of the PIPE PHY for Stratix V GX
transceiver. To learn more about this IP core, refer to the “PCI Express
PIPE PHY IP User Guide “ in the
Guide.
Specifies the maximum number of lanes supported. The ×8
configuration is only supported in the MegaWizard Plug-In Manager flow
for Stratix II GX and the hard IP implementations in the Arria II GX,
HardCopy IV GX, and Stratix IV GX and devices.
for an explanation of these settings.
Description
Altera Transceiver PHY IP Core User
December 2010 Altera Corporation
Chapter 14, External PHYs
Chapter 3: Parameter Settings
ALTGX Transceiver
System Settings