IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 212

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

13–6
Table 13–1. Dynamically Reconfigurable Registers in the Hard IP Implementation (Part 5 of 7)
PCI Express Compiler User Guide
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
Address
Bits
15:10 MSI-X PBA Offset.
15:13
15:7 MSI-X table size
15:5 MIS-X Table Offset.
15:0 Reserved.
15:0 Reserved.
15:0 Reserved.
15:0 Reserved.
15:8 Number of NFTS for separate clock in Gen2 rate.
12:9
15:3 Reserved.
1:0 Reserved.
4:2 MSI-X Table BIR.
3:0 Reserved.
7:4 Number of EIE symbols before NFTS.
7:0 Number of NFTS for common clock in Gen2 rate.
2:0
8 Selectable de-emphasis.
PCIe Capability Version.
L0s exit latency for common clock.
L0s exit latency for separate clock.
b’0000: Core is compliant to PCIe Specification 1.0a or
1.1.
b’0001: Core is compliant to PCIe Specification 1.0a or
1.1.
b’0010: Core is compliant to PCIe Specification 2.0.
Gen1: ( N_FTS (of separate clock) + 1 (for the SKIPOS)
) * 4 * 10 * UI (UI = 0.4 ns).
Gen2: [ ( N_FTS2 (of separate clock) + 1 (for the
SKIPOS) ) * 4 + 8 (max number of received EIE) ] * 10
* UI (UI = 0.2 ns).
Gen1: ( N_FTS (of separate clock) + 1 (for the SKIPOS)
) * 4 * 10 * UI (UI = 0.4 ns).
Gen2: [ ( N_FTS2 (of separate clock) + 1 (for the
SKIPOS) ) * 4 + 8 (max number of received EIE) ] * 10
* UI (UI = 0.2 ns).
b’000 – Less than 64 ns.
b’001 – 64 ns to less than 128 ns.
b’010 – 128 ns to less than 256 ns.
b’011 – 256 ns to less than 512 ns.
b’100 – 512 ns to less than 1 µs.
b’101 – 1 µs to less than 2 µs.
b’110 – 2 µs to 4 µs.
b’111 – More than 4 µs.
Description
Chapter 13: Reconfiguration and Offset Cancellation
b’11111111
b’11111111
Default
0x0000
b’0100
b’0010
Value
b’110
b’110
b’0
b’0
b’0
b’0
b’0
b’0
b’0
b’0
b’0
—
December 2010 Altera Corporation
Table 6–5 on page
MSI-X Capability
Structure
Table 6–5 on page
MSI-X Capability
Structure
Table 6–8 on page
Link Control register 2
Table 6–8 on page
PCI Express capability
register
Table 6–8 on page
Link Capability register
Table 6–8 on page
Link Capability register
Additional Information
Dynamic Reconfiguration
—
6–4,
6–4,
6–5,
6–5,
6–5,
6–5,