IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 259

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Root Port BFM
December 2010 Altera Corporation
Besides the ebfm_cfg_rp_ep procedure in altpcietb_bfm_configure, routines to read
and write endpoint configuration space registers directly are available in the
altpcietb_bfm_rdwr VHDL package or Verilog HDL include file. After the
ebfm_cfg_rp_ep procedure is run the PCI Express I/O and Memory Spaces have the
layout as described in the following three figures. The memory space layout is
dependent on the value of the addr_map_4GB_limit input parameter. If
addr_map_4GB_limit is 1 the resulting memory space map is shown in
Figure 15–7. Memory Space Layout—4 GByte Limit
0x001F FFC0
0xFFFF FFFF
0x001F FF80
0x0000 0000
0x0020 0000
Addr
not writable by user calls
not writable by user calls
Endpoint Memory Space
(Prefetchable 32 -bit and
Used by BFM routines
Used by BFM routines
Root Complex Shared
Configuration Scratch
Prefetchable Memory
Assigned Smallest to
Assigned Smallest to
Endpoint Non
Space BARs
or endpoint
or endpoint
BAR Table
Memory
Unused
Largest
Largest
Space
64-
BARs
bit)
-
,
,
PCI Express Compiler User Guide
Figure
15–7.
15–31