IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 328

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

B–22
Figure B–19. TX 64-Bit Memory Write Request Waveform
PCI Express Compiler User Guide
Descriptor
Signals
Data
Signals
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
In clock cycle five, the IP core asserts tx_ws a second time to throttle the flow of data
because priority was not given immediately to this virtual channel. Priority was given
to either a pending data link layer packet, a configuration completion, or another
virtual channel. The tx_err is not available in the ×8 IP core.
Transmit Request Can Remain Asserted Between Transaction Layer Packets
In this example, the application transmits a 64-bit memory read transaction followed
by a 64-bit memory write transaction. Address bit 2 is set to 0. Refer to
In clock cycle four, tx_req is not deasserted between transaction layer packets.
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
clk
1
2
MEMWR64
3
DW 1
DW 0
4
5
6
7
DW 3
DW 2
8
9
December 2010 Altera Corporation
DW 5
DW 4
Descriptor/Data Interface
11
Figure
DW 7
DW 6
B–20.
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