EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 301
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Contents
Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices
Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices
Altera Corporation
Introduction ............................................................................................................................................ 8–1
10-Gigabit Ethernet ................................................................................................................................ 8–1
Interfaces ................................................................................................................................................. 8–5
I/O Characteristics for XSBI, XGMII & XAUI ................................................................................. 8–21
Introduction ............................................................................................................................................ 9–1
Introduction .......................................................................................................................................... 10–1
General Architecture ........................................................................................................................... 10–1
TriMatrix Memory ............................................................................................................................... 10–8
DSP Block ............................................................................................................................................ 10–16
PLLs & Clock Networks ................................................................................................................... 10–18
I/O Structure ...................................................................................................................................... 10–25
Configuration ..................................................................................................................................... 10–30
Related Links ..................................................................................................................................... 8–1
XSBI .................................................................................................................................................... 8–5
XGMII ............................................................................................................................................... 8–13
XAUI ................................................................................................................................................. 8–19
Software Implementation .............................................................................................................. 8–22
AC/DC Specifications ................................................................................................................... 8–22
10-Gigabit Ethernet MAC Core .................................................................................................... 8–24
Conclusion ....................................................................................................................................... 8–25
System Topology .............................................................................................................................. 9–3
Interface Implementation in Stratix & Stratix GX Devices ......................................................... 9–5
AC Timing Specifications .............................................................................................................. 9–10
Electrical Specifications ................................................................................................................. 9–12
Software Implementation .............................................................................................................. 9–13
Conclusion ....................................................................................................................................... 9–13
Logic Elements ................................................................................................................................ 10–2
MultiTrack Interconnect ................................................................................................................ 10–3
DirectDrive Technology ................................................................................................................ 10–4
Architectural Element Names ...................................................................................................... 10–5
Same-Port Read-During-Write Mode ........................................................................................ 10–10
Mixed-Port Read-During-Write Mode ...................................................................................... 10–11
Memory Megafunctions .............................................................................................................. 10–12
FIFO Conditions ........................................................................................................................... 10–13
Design Migration Mode in Quartus II Software ...................................................................... 10–13
DSP Block Megafunctions ........................................................................................................... 10–16
Clock Networks ............................................................................................................................ 10–18
PLLs ................................................................................................................................................ 10–19
External RAM Interfacing ........................................................................................................... 10–25
I/O Standard Support ................................................................................................................. 10–26
High-Speed Differential I/O Standards .................................................................................... 10–26
altlvds Megafunction ................................................................................................................... 10–29
Contents
ix
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