EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 658
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Interfaces
8–14
Stratix Device Handbook, Volume 2
Figure 8–10. XGMII Functional Block Diagram
The 32 TXD and four TXC signals as well as the 32 RXD and four RXC
signals are organized into four data lanes. The four lanes in each direction
share a common clock (TX_CLK for transmit and RX_CLK for receive). The
four lanes are used in round-robin sequence to carry an octet stream
(8 bits of data per lane). The reconciliation sublayer generates continuous
data or control characters on the transmit path and expects continuous
data or control characters on the receive path.
Implementation
XGMII uses the 1.5-V HSTL I/O standard. Stratix and Stratix GX devices
support the 1.5-V HSTL Class I and Class II I/O standard (EIA/JESD8-6).
The standard requires a differential input with an external reference
voltage (V
which termination resistors are connected. The HSTL Class I standard
requires a 1.5-V V
Stratix GX devices.
Figure 8–11
XGMII.
PCS
REF
tx_data[15..0]
shows the 32-bit full-duplex 1.5-V HSTL implementation of
TXD[31..0]
) of 0.75 V, as well as a termination voltage V
CCIO
TXC[3..0]
Transmit
PCS
voltage, which is supported by Stratix and
RX_CLK
PMA
XSBI
XGMII
TX_CLK
Receive
RXC[3..0]
PCS
RXD[31..0]
rx_data[15..0]
Altera Corporation
TT
of 0.75 V, to
July 2005
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