EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 686

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

General Architecture
10–2
Stratix Device Handbook, Volume 2
Register chain interconnects Direct path between the register output
Look-up table (LUT) chain
interconnects
Register-to-LUT feedback
path
Dynamic arithmetic mode
Carry-select chain
Asynchronous clear and
asynchronous preset
function
Table 10–1. Stratix & Stratix GX LE Features
Feature
Logic Elements
Stratix and Stratix GX device LEs include several new, advanced features
that improve design performance and reduce logic resource consumption
(see
LE features to improve device utilization.
In addition to the new LE features described in
enhancements to the chains that connect LEs together. Carry chains are
implemented vertically in Stratix and Stratix GX devices, instead of
horizontally as in APEX II and APEX 20K devices, and continue across
rows, instead of across columns, as shown in
the Stratix and Stratix GX architectures do not support the cascade
primitive. Therefore, the Quartus II Compiler automatically converts
of an LE and the register input of an
adjacent LE within the same logic array
block (LAB)
Direct path between the combinatorial
output of an LE and the fast LUT input
of an adjacent LE within the same LAB
Allows the register output to feed back
into the LUT of the same LE, such that
the register is packed with its own fan-
out LUT
Uses one set of LEs for implementing
both an adder and subtractor
Calculates outputs for a possible carry-
in of 1 or 0 in parallel
Supports direct asynchronous clear
and preset functions
Table
10–1). The Quartus II software automatically uses these new
Function
implementation
resources within an LAB
cascade together for high-speed wide
fan-in functions, such as wide
operations
faster performance
that switch between addition and
subtraction frequently, such as
correlators
both a carry-in of 1 or 0
for high-speed operations, such as
counters, adders, and comparators
resources to implement NOT-gate
push-back
Conserves LE resources
Provides fast shift register
Saves local interconnect routing
Allows LUTs within the same LAB to
Bypasses local interconnect for
Enhanced register packing mode
Uses resources more efficiently
Improves performance for functions
Gives immediate access to result for
Increases speed of carry functions
Conserves LE resources
Does not require additional logic
Figure
Table
Benefit
10–1. Also note that
10–1, there are
Altera Corporation
July 2005
XOR