EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 330
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
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3 000
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Enhanced PLLs
Figure 1–9. Low-Bandwidth PLL Lock Time
1–20
Stratix Device Handbook, Volume 2
Frequency (MHz)
125
160
155
150
145
140
135
130
120
0
finite range to customize the PLL characteristics for a particular
application. Applications that require clock switchover (such as TDMA,
frequency hopping wireless, and redundant clocking) can benefit from
the programmable bandwidth feature of the Stratix and Stratix GX PLLs.
The bandwidth and stability of such a system is determined by a number
of factors including the charge pump current, the loop filter resistor
value, the high-frequency capacitor value (in the loop filter), and the m-
counter value. You can use the Quartus II software to control these factors
and to set the bandwidth to the desired value within a given range.
You can set the bandwidth to the appropriate value to balance the need
for jitter filtering and lock time.
a low- and high-bandwidth PLL, respectively, as it locks onto the input
clock.
5
Lock Time = 8 μs
Time (μs)
Figures 1–9
10
and
1–10
show the output of
Altera Corporation
July 2005
15
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