EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 657
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 657 of 864
- Download datasheet (11Mb)
Altera Corporation
July 2005
PMA_RX_CLK
Data set-up time (T
Data hold time (T
PCS sampling window
RSKM (WAN)
RSKM (LAN)
Table 8–5. PCS Receiver Timing Specifications (Part 2 of 2)
duty cycle
hold
setup
Parameter
)
)
XGMII
The purpose of XGMII is to provide a simple, inexpensive, and easy to
implement interconnection between the MAC sublayer and the PHY.
Though XGMII is an optional interface, it is used extensively in the
10-Gigabit Ethernet standard as the basis for the specification. The
conversion between the parallel data paths of XGMII and the serial MAC
data stream is carried out by the reconciliation sublayer. The
reconciliation sublayer maps the signal set provided at the XGMII to the
physical layer signaling (PLS) service primitives provided at the MAC.
XGMII supports a 10-Gbps MAC data rate.
Functional Description
The XGMII is composed of independent transmit and receive paths. Each
direction uses 32 data signals, TXD[31..0] and RXD[31..0], 4 control
signals, TXC[3..0] and RXC[3..0], and a clock TX_CLK and RX_CLK.
Figure 8–10
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
shows the XGMII functional block diagram.
Min
300
300
600
45
Value
Typ
Stratix Device Handbook, Volume 2
Max
304
276
55
Unit
ps
ps
ps
ps
ps
%
8–13
Related parts for EP1S10F780I6N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: