EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 419
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number
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Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
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3 000
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Figure 3–12. DQ Configuration in Stratix & Stratix GX IOE
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
June 2006
Logic Array
You can use the altdq megafunction to generate the DQ signals.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before the OE register A
The outclock signal is phase shifted –90° from the system clock.
The shifted DQS signal must be inverted before going to the IOE. The inversion is automatic if you use the altdq
megafunction to generate the DQ signals.
Figure
3–12:
dataout_h
(4)
dataout_l
inclock (from DQS bus)
(2)
datain_h
outclock (3)
OE
datain_l
OE
during compilation.
Latch C
Q
Latch
ENA
TCH
Output Register A
Output Register B
External Memory Interfaces in Stratix & Stratix GX Devices
I
D
LA
OE Register A
DFF
DFF
DFF
D
D
D
neg_reg_out
Q
Q
Q
OE
Note (1)
O
O
Input Register A
Input Register B
Q
Q
DFF
DFF
Stratix Device Handbook, Volume 2
D
D
0
1
I
I
TRI
DQ Pin
3–23
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