EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 394
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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EP1S10F780I6N
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Read-During-Write Operation at the Same Address
2–26
Stratix Device Handbook, Volume 2
When using byte enables in true dual-port RAM mode, the outputs for
the masked bytes on the same port are unknown. (See
page
Figure 2–15. Same-Port Read-During-Write Functionality
Note to
(1)
Mixed-Port Read-During-Write Mode
This mode is used when a RAM in simple or true dual-port mode has one
port reading and the other port writing to the same address location with
the same clock.
The READ_DURING_WRITE_MODE_MIXED_PORTS parameter for M512
and M4K memory blocks determines whether to output the old data at
the address or a “don’t care” value. Setting this parameter to OLD_DATA
outputs the old data at that address. Setting this parameter to DONT_CARE
outputs a “don’t care” or unknown value. See
sample functional waveforms showing this operation. These figures
assume that the outputs are not registered.
The DONT_CARE setting allows memory implementation in any TriMatrix
memory block. The OLD_DATA setting restricts memory implementation
to only M512 or M4K memory blocks. Selecting DONT_CARE gives the
compiler more flexibility when placing memory functions into TriMatrix
memory.
Outputs are not registered.
2–6.) The non-masked bytes are read out as shown in
Figure
2–15:
data_out
data_in
inclock
wren
Old
A
A
Figures 2–16
B
Note (1)
Figure 2–1 on
Altera Corporation
Figure
and
July 2005
2–17
2–15.
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