EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 333
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Manufacturer
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Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
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3 000
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Figure 1–12. Effect of High Bandwidth on Clock Switchover
Altera Corporation
July 2005
Frequency (MHz)
160
155
150
145
140
135
130
125
0
2
Implementation
Traditionally, external components such as the VCO or loop filter control
a PLL’s bandwidth. Most loop filters are made up of passive components,
such as resistors and capacitors, which take up unnecessary board space
and increase cost. With Stratix and Stratix GX device enhanced PLLs, all
the components are contained within the device to increase performance
and decrease cost.
Stratix and Stratix GX device enhanced PLLs implement programmable
bandwidth by giving you control of the charge pump current and loop
filter resistor (R) and high-frequency capacitor (C
Table
ranges from approximately 150 kHz to 2 MHz.
Initial Lock
4
1–8). The Stratix and Stratix GX device enhanced PLL bandwidth
6
General-Purpose PLLs in Stratix & Stratix GX Devices
8
Time (μs)
Input Clock Stops
10
Switchover
12
Stratix Device Handbook, Volume 2
14
h
) values (see
Re-lock
16
18
1–23
20
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