EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 663

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
Timing
XGMII signals must meet the timing requirements shown in
Make all XGMII timing measurements at the driver output (shown in
Figure
specified relative to the V
Figure 8–14. XGMII Timing Diagram
Table 8–8
Stratix and Stratix GX devices support DDR data with clock rates of up to
200 MHz, well above the XGMII clock rate of 156.25 MHz. For the HSTL
Class I I/O standard, Stratix and Stratix GX device I/O drivers provide a
1.0-V/ns slew rate at the input buffer of the receiving device.
XAUI
XAUI (pronounced Zowie) is located between the XGMII at the
reconciliation sublayer and the XGMII at the PHY layer.
shows the location of XAUI. XAUI is designed to either extend or replace
XGMII in chip-to-chip applications of most Ethernet MAC to PHY
interconnects.
Note to
(1)
T
T
Table 8–8. XGMII Timing Specifications
setup
hold
RXC, RXD
TXC, TXD,
RX_CLK
The actual set-up and hold times will be made available after device
characterization is complete.
TX_CLK
Symbol
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
8–14) and a capacitive load from all sources of 20 pF that are
Table
shows the XGMII timing specifications.
t
setup
8–8:
Driver
IL
960
960
_AC(max) and V
t
hold
Note (1)
Stratix Device Handbook, Volume 2
t
setup
Receiver
480
480
IH
_AC(min) thresholds.
Figure 8–15
t
hold
V
V
Figure
V
V
IL
IH
IL
IH
_AC(max)
Unit
_AC(max)
_AC(min)
_AC(min)
ps
ps
8–14.
8–19