EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 752
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Quantity
Price
Company:
Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Configuration Schemes
Figure 11–18. PPA Timing Waveforms for Stratix & Stratix GX Devices
Notes to
(1)
(2)
(3)
(4)
11–34
Stratix Device Handbook, Volume 2
CONF_DONE
Upon power-up, nSTATUS is held low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
After configuration, the state of CS, nCS, nWS, and RDYnBSY depends on the design programmed into the Stratix or
Stratix GX device.
Device I/O pins are in user mode.
RDYnBSY
nSTATUS
Figure
DATA[7..0]
INIT_DONE
nCONFIG
nWS
nCS
User I/Os
CS
(
(
(
(
(
(
11–18:
1)
2)
3)
3)
3)
3)
t
t
CF2CD
t
CF2ST0
CFG
t
STATUS
t
CF2ST1
PPA Configuration Timing
Figure 11–18
for PPA configuration.
t
CF2WS
High-Z
t
CSSU
t
DSU
Byte 0
t
DH
shows the Stratix and Stratix GX device timing waveforms
t
WS2B
t
WSP
Byte 1
t
RDY2WS
Byte n Ð 1
t
CSSU
t
CSH
t
BUSY
Byte n
Altera Corporation
t
July 2005
CD2UM
(
(
(
(
(
4)
4)
4)
4)
4)
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