EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 607
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
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3 000
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Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Polyphase Decimation Filter Implementation
Figure 7–17
Figure 7–16
coefficients of the polyphase filters need to be cycled using the schedule
shown in
Table 7–13. Coefficient Loading Schedule for Polyphase Decimation Filter
(D=4)
Cycle of 4 Clock
1, 5,...
2, 6,...
3, 7,...
4, 8,...
Table
shows the decimation polyphase filter example of
as it would fit into Stratix or Stratix GX DSP blocks. The
7–13. The output y(n), is clocked using the 1 clock.
h(3), h(7), h(11), h(15)
h(2), h(6), h(10), h(14)
h(0), h(4), h(8), h(12)
h(1), h(5), h(9), h(13)
Coefficients to Load
Stratix Device Handbook, Volume 2
Corresponding RAM/ROM
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
7–29
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