EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 331
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
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3 000
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Figure 1–10. High-Bandwidth PLL Lock Time
Altera Corporation
July 2005
Frequency (MHz)
160
155
150
145
140
135
130
125
120
0
0.5
A high-bandwidth PLL may benefit a system with two cascaded PLLs. If
the first PLL uses spread spectrum (as user-induced jitter), the second
PLL needs a high bandwidth so it can track the jitter that is feeding it. A
low-bandwidth PLL may, in this case, lose lock due to the spread
spectrum-induced jitter on the input clock.
A low-bandwidth PLL may benefit a system using clock switchover.
When the clock switchover happens, the PLL input temporarily stops. A
low-bandwidth PLL would react more slowly to changes to its input
clock and take longer to drift to a lower frequency (caused by the input
stopping) than a high-bandwidth PLL.
demonstrate this property.
The two plots show the effects of clock switchover with a low- or high-
bandwidth PLL. When the clock switchover happens, the output of the
low-bandwidth PLL (see
slower than the high-bandwidth PLL output (see
1.0
1.5
2.0
General-Purpose PLLs in Stratix & Stratix GX Devices
Figure
Time (μs)
2.5
1–11) drifts to lower frequency much
3.0
Stratix Device Handbook, Volume 2
Figures 1–11
3.5
Lock Time = 4 μs
Figures
and
4.0
1–12
1–12).
4.5
1–21
5.0
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