EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 465

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
June 2006
Figure 4–22. Current Draw Limitation Guidelines
Any 10 consecutive I/O pads cannot exceed 200 mA in thermally
enhanced FineLine BGA and thermally enhanced BGA cavity up
packages or 164 mA in non-thermally enhanced cavity up and non-
thermally enhanced FineLine BGA packages.
For example, consider a case where a group of 10 consecutive pads are
configured as follows for a thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up package:
■
■
■
In this case, the total current draw for these 10 consecutive I/O pads
would be:
(# of SSTL-3 Class I pads
(# of GTL+ output pads
In the above example, the total current draw for all 10 consecutive I/O
pads is less than 200 mA.
Number of SSTL-3 Class I output pads = 3
Number of GTL+ output pads = 4
The rest of the surrounding I/O pads in the consecutive group of 10
are unused
I/O Pin Sequence
GND
of an I/O Bank
VCC
Selectable I/O Standards in Stratix & Stratix GX Devices
34 mA) = (3
8 mA) +
Stratix Device Handbook, Volume 2
8 mA) + (4
Any 10 Consecutive I/O Pins,
34 mA) = 160 mA
4–37