EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 505
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 505 of 864
- Download datasheet (11Mb)
Altera Corporation
July 2005
t
Timing unit interval (TUI)
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak)
Output jitter (peak-to-peak)
t
t
FALL
HSDR
DUTY
LOCK
Table 5–6. High-Speed Timing Specifications & Terminology (Part 2 of 2)
High-Speed Timing Specification
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t
Maximum LVDS data transfer rate (f
The timing difference between the fastest and slowest output edges,
including t
measurement.
The period of time during which the data must be valid in order for you to
capture it correctly. The setup and hold times determine the ideal strobe
position within the sampling window.
SW = t
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
SW
CO
(max) – t
High-Speed Differential I/O Interfaces in Stratix Devices
variation and clock skew. The clock is included in the TCCS
SW
(min).
C
/w).
Terminology
Stratix Device Handbook, Volume 2
HSDR
= 1/TUI).
5–33
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