EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 682
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Introduction
9–12
Stratix Device Handbook, Volume 2
RX_CLK
Data invalid window before the rising edge (T
Data invalid window after the rising edge (T
RX_CLK
Data set-up time (T
Data hold time (T
Framer sampling window
Receiver skew margin (RSKM)
Table 9–6. Framer Receiver Timing Specifications
(T
duty cycle
period
)
hold
setup
Parameter
)
)
Table 9–6
Electrical Specifications
SFI-4 uses LVDS as a high-speed data transfer mechanism to implement
the SFI-4 interface.
interface, which are based on the IEEE Std. 1596.3-1996 7 specification.
For more information on the voltage specification of LVDS I/O standards
in Stratix and Stratix GX devices, see the Stratix Device Family Data Sheet
section of the Stratix Device Handbook, Volume 1 and the High-Speed
Differential I/O Interfaces in Stratix Devices chapter or the Stratix GX Device
Family Data Sheet section of the Stratix GX Device Handbook, Volume 1 and
the High-Speed Differential I/O Interfaces in Stratix Devices chapter.
lists the timing specifications for the SFI-4 framer receiver.
cq_post
cq_pre
)
)
Table 9–7
Min
300
300
600
45
lists the DC electrical characteristics for the
Value
1,608
Typ
Max
200
200
304
55
Altera Corporation
July 2005
Unit
ps
ps
ps
ps
ps
ps
ps
%
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