EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 488
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Differential I/O Interface & Fast PLLs
Differential I/O
Interface & Fast
PLLs
5–16
Stratix Device Handbook, Volume 2
Stratix devices provide 16 dedicated global clocks, 8 dedicated fast
regional I/O pins, and up to 16 regional clocks (four per device quadrant)
that are fed from the dedicated global clock pins or PLL outputs. The 16
dedicated global clocks are driven either by global clock input pins that
support all I/O standards or from enhanced and fast PLL outputs.
Stratix devices use the fast PLLs to implement clock multiplication and
division to support the SERDES circuitry. The input clock is either
multiplied by the W feedback factor and/or divided by the J factor. The
resulting clocks are distributed to SERDES, local, or global clock lines.
Fast PLLs are placed in the center of the left and right sides for EP1S10 to
EP1S25 devices. For EP1S30 to EP1S80 devices, fast PLLs are placed in the
center of the left and right sides, as well as the device corners (see
Figure
SERDES in the rows above and below or top and bottom of the device as
shown in
5–13). These fast PLLs drive a dedicated clock network to the
Figure
5–13.
Altera Corporation
July 2005
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