EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 437
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 437 of 864
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Altera Corporation
June 2006
Figure 4–5. GTL+ Termination
CTT - EIA/JEDEC Standard JESD8-4
The CTT I/O standard is used for backplanes and memory bus interfaces.
The CTT standard defines the DC interface parameters for digital circuits
operating from 2.5- and 3.3-V power supplies. The CTT standard does not
require special circuitry to interface with LVTTL or LVCMOS devices
when the CTT driver is not terminated. The CTT standard requires a 1.5-V
V
support both input and output levels.
Figure 4–6. CTT Termination
SSTL-3 Class I & II - EIA/JEDEC Standard JESD8-8
The SSTL-3 I/O standard is a 3.3-V memory bus standard used for
applications such as high-speed SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-3 logic switching range of 0.0 to 3.3 V. The SSTL-3 standard specifies
an input voltage range of – 0.3 V V
V V
connected (see
support both input and output levels.
REF
REF
and a 1.5-V V
and a 1.5-V V
Output Buffer
Output Buffer
Figures 4–7
TT
Selectable I/O Standards in Stratix & Stratix GX Devices
V
TT
(see
TT
to which the series and termination resistors are
= 1.5 V
Figure
V
50 Ω
REF
and 4–8). Stratix and Stratix GX devices
V
REF
Z = 50 Ω
Z = 50 Ω
= 1.0 V
= 1.5 V
4–6). Stratix and Stratix GX devices
I
V
V
TT
TT
V
Stratix Device Handbook, Volume 2
= 1.5 V
CCIO
= 1.5 V
50 Ω
50 Ω
+ 0.3 V. SSTL-3 requires a 1.5-
Input Buffer
Input Buffer
4–9
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