EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 739

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 11–9. PS Timing Waveform for Stratix & Stratix GX Devices
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
July 2005
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is convenient.
DATA[] is available as user I/Os after configuration and the state of these pins depends on the dual-purpose pin
settings.
CONF_DONE (3)
Figure
nSTATUS (2)
INIT_DONE
nCONFIG
11–9:
User I/O
DCLK
DATA
t
t
CF2CD
CFG
t
FPP Configuration
Parallel configuration of Stratix and Stratix GX devices meets the
continuously increasing demand for faster configuration times. Stratix
and Stratix GX devices can receive byte-wide configuration data per clock
cycle, and guarantee a configuration time of less than 100 ms with a 100-
MHz configuration clock. Stratix and Stratix GX devices support
programming data bandwidth up to 800 megabits per second (Mbps) in
this mode. You can use parallel configuration with an EPC16, EPC8, or
EPC4 device, or a microprocessor.
This section discusses the following schemes for FPP configuration in
Stratix and Stratix GX devices:
■
■
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
FPP Configuration Using an Enhanced Configuration Device
FPP Configuration Using a Microprocessor
t
Bit 0 Bit 1 Bit 2 Bit 3
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
Bit n
Configuring Stratix & Stratix GX Devices
Note (1)
Stratix Device Handbook, Volume 2
t
CD2UM
User Mode
(4)
(4)
11–21