EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 374

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

TriMatrix Memory
Figure 2–1. Byte Enable Functional Waveform
Note to
(1)
2–6
Stratix Device Handbook, Volume 2
asynch_data_out
contents at a0
contents at a1
contents at a2
For more information on simulation output when a read-during-write occurs at the same address location, see
“Read-During-Write Operation at the Same Address” on page
address
Figure
inclock
byteena
data_in
wren
2–1:
XXXX
XX
an
FFFF
doutn
FFFF
Byte Enable Functional Waveform
Figure 2–1
the write operations of the RAM.
Notes to
(1)
(2)
Table 2–6. M-RAM Combined Byte Selection for 144 Mode (Part 2 of 2),
Notes
a0
10
FFFF
Any combination of byte enables is possible.
Byte enables can be used in the same manner with 8-bit words, i.e., in 16, 32,
64, and 128 modes.
ABXX
(1),
Table
(2)
shows how both the wren and the byteena signals control
ABCD
byteena_a
a1
01
2–6:
[12] = 1
[13] = 1
[14] = 1
[15] = 1
Note (1)
XXCD
11
a2
2–25.
ABCD
ABFF
a0
FFCD
ABFF
ABCD
a1
datain 144
XXXX
[116..108]
[125..117]
[134..126]
[143..135]
XX
FFCD
Altera Corporation
a2
July 2005
ABCD