EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 602

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Finite Impulse Response (FIR) Filters
7–24
Stratix Device Handbook, Volume 2
Polyphase Interpolation Filter Implementation Results
Table 7–11
implementation in a Stratix device shown in
Polyphase Interpolation Filter Design Example
Download the Interpolation FIR Filter (interpolation_fir.zip) design
example from the Design Examples section of the Altera web site at
www.altera.com.
Polyphase FIR Decimation Filters
A decimation filter can be used to decrease the sample rate. A decimation
filter is efficiently implemented with a polyphase FIR filter. DSP systems
frequently use polyphase filters because they simplify overall system
design and also reduce the number of computations per cycle required of
the hardware. This section first describes decimation filters and then how
to implement them as polyphase filters in Stratix devices. See the
“Polyphase FIR Interpolation Filters”
interpolation filters.
Decimation Filter Basics
A decimation filter decreases the output sample rate by a factor of D
through keeping only every D-th input sample. Consequently, the
samples at the output of the decimation filter are separated by D T
D/f
original signal, respectively.
decimation.
The signal needs to be low pass filtered before downsampling can begin
in order to avoid the reflections of the original spectrum from being
aliased back into the output signal.
Note to
(1)
Part
Utilization
Performance
Table 7–11. Polyphase Interpolation Filter Implementation Results
s
This refers to the performance of the DSP blocks, as well as the output clock rate.
The input rate is 60 MSPS, clocked in at 60MHz.
, where T
Table
shows the results of the polyphase interpolation filter
7–11:
s
and f
s
EP1S10F780
Lcell: 3/10570 (<1%)
DSP Block 9-bit elements: 8/48 (17%)
Memory bits: 288/920448 (<1%)
240 MHz
are the sample period and sample frequency of the
Figure 7–14
(1)
section for a discussion of
shows the concept of signal
Figure
7–13.
Altera Corporation
September 2004
s
=