EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 423
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Conclusion
Altera Corporation
June 2006
f
PLL
When using the Stratix and Stratix GX top and bottom I/O banks (I/O
banks 3, 4, 7, or 8) to interface with a DDR memory, at least one PLL with
two outputs is needed to generate the system clock and the write clock.
The system clock generates the DQS write signals, commands, and
addresses. The write clock is –90° shifted from the system clock and
generates the DQ signals during writes.
When using the Stratix and Stratix GX side I/O banks 1, 2, 5, or 6 to
interface with DDR SDRAM devices, two PLLs may be needed per I/O
bank for best performance. The side I/O banks do not have dedicated
circuitry, so one PLL captures data from the DDR SDRAM and another
PLL generates the write signals, commands, and addresses to the
DDR SDRAM device. Stratix and Stratix GX devices side I/O banks can
support DDR SDRAM up to 150 MHz.
For more information, see AN 342: Interfacing DDR SDRAM with Stratix
& Stratix GX Devices.
Stratix and Stratix GX devices support SDR SDRAM, DDR SDRAM,
RLDRAM II, QDR SDRAM, QDRII SRAM, and ZBT SRAM external
memories. Stratix and Stratix GX devices feature high-speed interfaces
that transfer data between external memory devices at up to
200 MHz/400 Mbps. Phase-shift circuitry in the Stratix and Stratix GX
devices allows you to ensure that clock edges are properly aligned.
External Memory Interfaces in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
3–27
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