EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 416
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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DDR Memory Support Overview
3–20
Stratix Device Handbook, Volume 2
DDR Registers
Each Stratix and Stratix GX IOE contains six registers and one latch. Two
registers and a latch are used for input, two registers are used for output,
and two registers are used for output enable control. The second output
enable register provides the write preamble for the DQS strobe in the
DDR external memory interfaces. This negative-edge output enable
register extends the high-impedance state of the pin by a half clock cycle
to provide the external memory's DQS preamble time specification.
Figure 3–10
Stratix GX IOE and
extends the DQS high impedance state by half a clock cycle during a write
operation.
shows the six registers and the latch in the Stratix and
Figure 3–11
shows how the second OE register
Altera Corporation
June 2006
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