EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 766
EP1S10F780I6N
Manufacturer Part Number
EP1S10F780I6N
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S10F780I6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 766 of 864
- Download datasheet (11Mb)
Configuration Schemes
Figure 11–26. Jam Player Flow Diagram (Part 2 of 2)
11–48
Stratix Device Handbook, Volume 2
Shift-DR
Set TMS to 0
and Pulse TCK,
Write TDI, and
Store TDO
DR Length
Loop<
T
F
Execution of a Jam program starts at the beginning of the program. The
program flow is controlled using GOTO, CALL/RETURN, and FOR/NEXT
structures. The GOTO and CALL statements see labels that are symbolic
names for program statements located elsewhere in the Jam program. The
language itself enforces almost no constraints on the organizational
structure or control flow of a program.
1
and Pulse TCK
and Store TDO
Set TMS to 1
and Pulse TCK
and Pulse TCK
Set TMS to 0
Set TMS to 1
TDO Value
Correct
Switch
T
Exit1-DR
Update-IR
Run-Test/Idle
The Jam language does not support linking multiple Jam
programs together or including the contents of another file into
a Jam program.
Compare
F
Report
Error
Continued from
Part 1 of
Flow Diagram
Case[]
Set TMS to 1
and Pulse TCK
and Store TDO
Set TMS to 1
and Pulse TCK
Set TMS to 0
and Pulse TCK
Capture
Default
Switch
Exit1-DR
Update-IR
Run-Test/Idle
F
Set TMS to 0
and Pulse TCK,
Write TDI, and
Store TDO
DR Length
Set TMS to 1
and Pulse TCK
and Store TDO
Set TMS to 1
and Pulse TCK
Set TMS to 0
and Pulse TCK
Loop<
Switch
T
Exit1-DR
Update-IR
Run-Test/Idle
Altera Corporation
F
Set TMS to 0
and Pulse TCK
and Write TDI
DR Length
Loop<
T
July 2005
Related parts for EP1S10F780I6N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: