MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 108

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocking
1
Table 74
conditions (see
108
1
2
3
PCI Express1, 2
SATA1, 2
e300 core frequency (core_clk)
Coherent system bus frequency (csb_clk)
DDR2 memory bus frequency (MCK)
DDR1 memory bus frequency (MCK)
Local bus frequency (LCLKn)
Local bus controller frequency (lbc_clk)
PCI input frequency (CLKIN or PCI_CLK)
eTSEC frequency
Security encryption controller frequency
USB controller frequency
eSDHC controller frequency
PCI Express controller frequency
SATA controller frequency
Note:
MCK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The
value of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core, USB
modules, SATA, and eSDHC will not exceed their respective value listed in this table.
csb_clk frequency (depending on RCWLR[LBCM]).
This only applies to I
The CLKIN frequency, RCWLR[SPMF], and RCWLR[COREPLL] settings must be chosen such that the resulting csb_clk,
The DDR data rate is 2× the DDR memory bus frequency.
The local bus frequency is ½, ¼, or 1/8 of the lbiu_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2× the
provides the operating frequencies for the TePBGA II package under recommended operating
Unit
Table
2
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
C1 (I
3).
Parameter
2
C2 clock is not configurable).
3
Table 73. Configurable Clock Units (continued)
Table 74. Operating Frequencies for TePBGA II
2
2
1
Default Frequency
csb_clk/3
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
Minimum Operating
Frequency (MHz)
333
133
125
167
25
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—
—
—
—
—
—
—
Options
Maximum Operating
Freescale Semiconductor
Frequency (MHz)
800
400
200
333
133
400
400
200
200
200
400
200
66